View NCP5393A_4548769.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

The NCP5393A is a multiphase synchronous buck regulator controller designed to power the Core and Northbridge of an AMD microprocessor. The controller has a user configurable two, three, or four phase regulator for the Core and an independent single phase regulator to power the microprocessor Northbridge. The NCP5393A incorporates differential voltage sensing, differential phase current sensing, optional load-line voltage positioning, and programmable VDD and VDDNB offsets to provide accurately regulated power parallel- and serial-VID AMD processors. Dual-edge multiphase modulation provides the fastest initial response to dynamic load events. This reduces system cost by requiring less bulk and ceramic output capacitance to meet transient regulation specifications. High performance operational error amplifiers are provided to simplify compensation of the VDD and VDDNB regulators. Dynamic Reference Injection further simplifies loop compensation by eliminating the need to compromise between response to load transients and response to VID code changes.
Features
NCP5393A Product Preview 2/3/4-Phase Controller for CPU Applications
http://onsemi.com MARKING DIAGRAM
1
1 48 QFN48, 7x7 CASE 485AJ A WL YY WW G
NCP5393A AWLYYWWG
* * * * * * * * * * * * * * * * * * * * *
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
Meets AMD's Hybrid VR Specifications Up to Four VDD Phases Single-Phase VDDNB Controller Dual-Edge PWM for Fastest Initial Response to Transient Loading High Performance Operational Error Amplifiers Internal Soft Start and Slew Rate Limiting Dynamic Reference Injection (Patent #US07057381) DAC Range from 12.5 mV to 1.55 V $0.5% DAC Accuracy fro 0.8 V to 1.55 V VDD and VDD Offset Ranges 0 mV - 800 mV True Differential Remote Voltage Sense Amplifiers Phase-to-Phase IDD Current Balancing Differential Current Sense Amplifiers for Each Phase of Each Output "Lossless" Inductor Current Sensing for VDD and VDDNB Outputs Supports Load Lines (Droop) for VDD and VDDNB Outputs Oscillator Range of 100 kHz - 1 MHz Tracking Over Voltage Protection Output Inductor DCR-Based Over Current Protection for VDD and VDDNB Outputs Guaranteed Startup into Precharged Loads Temperature Range: 0C to 70C This is a Pb-Free Device
ORDERING INFORMATION
Device NCP5393AMNR2G Package QFN48 (Pb-Free) Shipping 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Applications
* Desktop Processors * Server Processors * High-End Notebook PCs
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.
(c) Semiconductor Components Industries, LLC, 2008
August, 2008 - Rev. P0
1
Publication Order Number: NCP5393A/D
NCP5393A
G1 G2 G3 G4 NB_G DRVON NB_DRVON PWRGOOD SVD/VID2 SVC/VID3 ENABLE PWROK 48 1 VCCA GND COMP FB DROOP VS+ VS- OFFSET DIFFOUT VFIX 12VMON PSI_L
VID1 VID0 NB_COMP NB_FB NB_DROOP NB_VS+ NB_VS- NB_OFFSET NB_DIFFOUT ROSC VID5 VID4
CS1 CS1N CS2 CS2N CS3 CS3N CS4 CS4N ILIM VCCB NB_CS NB_CSN
Figure 1. Pinout
http://onsemi.com
2
NCP5393A
NB_VS+ NB_VS- NB_DIFFOUT
- + Diff Amp
+ - PWM_NB HI-Z OVP FAULT VDD PSI_L MID
NB_G
NB_FB
1.3 V
+ - Error Amp ILIMIT_NB + - ILIMIT_NB = ILIMIT_VDD/N (N = VDD phase count) NB_SRL NB_DAC NB_VS+ NB_VS-
NB_COMP
NB_DROOP Gain = 1 Droop Amplifier NB_CS NB_CSN + - Gain = 6 NB Oscillator 1.3 V +
NB REGULATOR Fault Logic and Monitor Circuits
NB_DRVON
NORMAL OPERATION BOOT_VID & VFIX MODES NB_SRL OUT NB Slew Rate Limit
NB OFFSET SCALING X NB_DAC OUT + NB
NB_OFFSET
PWRGOOD PWROK VID0 VID1 VID2/SVD VID3/SVC VID4 VID5 PSI_L OFFSET
fNB = 1.27 x fVDD
VDD Slew Rate Limit VS- VS+ DIFFOUT - + Diff Amp VDD_SRL OUT
PVI/SVI HYBRID INTERFACE VDD_DAC OUT +
VDD
NORMAL OPERATION BOOT_VID & VFIX MODES
FB
1.3 V
+ - Error Amp
X VDD OFFSET SCALING
FLAG
COMP
GND
DROOP Gain = 1 Droop Amplifier CS1 CS1N CS2 CS2N CS3 CS3N CS4 CS4N + - Gain = 6 + - Gain = 6 + - Gain = 6 + - Gain = 6 VDD Oscillator ROSC ILIMIT_VDD + - VDD REGULATOR Fault Logic 3-Phase Detection and Monitor Circuits DRVON + + 1.3 V + - PWM1 + - PWM2 + - PMW3 + - PWM4 SHED OVP VDD PSI_L
HI-Z
MID
G1 G2
+ +
HI-Z
MID
HI-Z HI-Z
MID MID
G3
+
G4
ILIM ENABLE VCCA VCCB + + - 5V UVLO 4.25V/4.05V 12VMON + - 12V UVLO 8.5V/7.5V NCP5393A
VDD_SRL VDD_DAC VS+ VS-
Figure 2. NCP5393A Block Diagram
http://onsemi.com
3
NCP5393A
TBD
Figure 3. NCP5393A Configured for 3 + 1 Phases, with Optional Droop http://onsemi.com
4
TBD
NCP5393A
NCP5393A PIN DESCRIPTIONS
Pin No. 1 2 3 4 5 6 7 8 9 10 Symbol VCCA GND COMP FB DROOP VS+ VS- OFFSET DIFFOUT VFIX Description 5 V supply pin for the NCP5393A. The VCC bypassing capacitance must be connected between this pin and GND (preferably returned to the package flag). Small-signal power supply return. This pin should be tied directly to the package flag (exposed pad). Output of the voltage error amplifier for the VDD regulator. Voltage error amplifier inverting input for the VDD regulator. Voltage output signal proportional to total current drawn from the VDD regulator. Used when load line operation ("droop") is desired. Non-inverting input to the differential remote sense amplifier for the VDD regulator. Inverting input to the differential remote sense amplifier for the VDD regulator. Input for offset voltage to be added to the VDD DAC's output voltage. Ground this pin for zero VDD offset. Output of the differential remote sense amplifier for the VDD regulator. When pulled low, this pin causes the levels on the SVC (VID3) and SVD (VID2) pins to be decoded as a two-bit DAC code, which controls the VDD and VDDNB outputs. Internally pulled high by 5 mA to VCC UVLO monitor input for the 12 V power rail. Determines number of phases operating in PSI_L mode. Phase shed count is locked upon ENABLE assertion. After soft-start, becomes power saving control in PVID mode. Low = phase shed operation, High = normal operation. Non-inverting input to current sense amplifier #1 for the VDD regulator. See Table: "Pin Connections vs. Phase Count" Inverting input to current sense amplifier #1 for the VDD regulator. See Table: "Pin Connections vs. Phase Count" Non-inverting input to current sense amplifier #2 for the VDD regulator. See Table: "Pin Connections vs. Phase Count" Inverting input to current sense amplifier #2 for the VDD regulator. See Table: "Pin Connections vs. Phase Count" Non-inverting input to current sense amplifier #3 for the VDD regulator. See Table: "Pin Connections vs. Phase Count" Inverting input to current sense amplifier #3 for the VDD regulator. See Table: "Pin Connections vs. Phase Count" Non-inverting input to current sense amplifier #4 for the VDD regulator. See Table: "Pin Connections vs. Phase Count" Inverting input to current sense amplifier #4 for the VDD regulator. See Table: "Pin Connections vs. Phase Count" Overcurrent shutdown threshold for VDD and VDDNB. A resistor divider from ROSC to GND is typically used to develop an appropriate voltage on ILIM. 5 V supply pin. Tie this pin to VCCA (Pin 1). Non-inverting input to the current sense amplifier for the VDDNB regulator Inverting input to the current sense amplifier for the VDDNB regulator Parallel Voltage ID DAC Input 4. Not used in SVI mode. Parallel Voltage ID DAC Input 5. Not used in SVI mode. A resistance from this pin to ground programs the VDD and VDDNB oscillator frequencies. This pin supplies a trimmed output voltage of 2 V. Output of the differential remote sense amplifier for the VDDNB regulator. Input for offset voltage to be added to the VDDNB DAC's output voltage. Ground this pin for zero VDDNB offset. Inverting input to the differential remote sense amplifier for the VDDNB regulator. Non-inverting input to the differential remote sense amplifier for the VDDNB regulator.
11 12
12VMON PSI_L
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CS1 CS1N CS2 CS2N CS3 CS3N CS4 CS4N ILIM VCCB NB_CS NB_CSN VID4 VID5 ROSC NB_DIFFOUT NB_OFFSET NB_VS- NB_VS+
http://onsemi.com
5
NCP5393A
NCP5393A PIN DESCRIPTIONS
Pin No. 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 FLAG Symbol NB_DROOP NB_FB NB_COMP VID0 VID1 PWROK ENABLE VID3/SVC VID2/SVD PWRGOOD NB_DRVON DRVON NB_G G4 G3 G2 G1 PGND Description Voltage output signal proportional to total current drawn from the VDDNB regulator. Used when load line operation ("droop") is desired. Voltage error amplifier inverting input for the VDDNB regulator. Output of the voltage error amplifier for the VDDNB regulator. Parallel Voltage ID DAC Input 0. Not used in SVI mode. Parallel Voltage ID DAC Input 1. Also used for PVI or SVI mode selection. System power supplies status input. Used in SVI mode only. High = Run, Low = Standby/Reset. Parallel Voltage ID DAC Input 1. Also used in SVI mode. Parallel Voltage ID DAC Input 1. Also used in SVI mode. Open drain output. High indicates that the active output(s) are within specification. Internally pulled high by 5 mA to VCC Bidirectional Gate Drive Enable to the gate driver for the VDDNB regulator. Bidirectional Gate Drive Enable to gate drivers for the VDD regulator. PWM output to the VDDNB gate driver. PWM output #4. See Table: "Pin Connections vs. Phase Count" PWM output #3. See Table: "Pin Connections vs. Phase Count" PWM output #2. See Table: "Pin Connections vs. Phase Count" PWM output #1. See Table: "Pin Connections vs. Phase Count" High-current power supply return via metal pad (flag) underneath package. The package flag should be tied directly to Pin 2.
PIN CONNECTIONS VS. PHASE COUNT
Number of Phases 4 3 2 G4 Phase 4 Out Tie to GND Tie to GND G3 Phase 3 Out Phase 3 Out Phase 2 Out G2 Phase 2 Out Phase 2 Out Tie to GND G1 Phase 1 Out Phase 1 Out Phase 1 Out CS4 & CS4N Phase 4 CS Input Tie to GND or VDD Tie to GND or VDD CS3 & CS3N Phase 3 CS Input Phase 3 CS Input Phase 2 CS input CS2 & CS2N Phase 2 CS Input Phase 2 CS Input Tie to GND or VDD CS1 & CS1N Phase 1 CS Input Phase 1 CS Input Phase 1 CS Input
http://onsemi.com
6
NCP5393A
ABSOLUTE MAXIMUM RATINGS ELECTRICAL INFORMATION
Pin Symbol 12VMON VCC COMP, NB_COMP DROOP, NB_DROOP DIFFOUT, NB_DIFFOUT DRVON, NB_DRVON PWRGOOD VS+, NB_VS+ VS-, NB_VS- ROSC All Other Pins VMAX 13.2 V 7.0 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 3V 0.3 V 5.5 V 5.5 V VMIN -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V ISOURCE N/A N/A 10 mA 5 mA 20 mA 5 mA N/A 1 mA 1 mA 1 mA N/A ISINK 50 mA 10 mA 10 mA 5 mA 20 mA 10 mA 20 mA 1 mA 1 mA N/A N/A
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: All signals are referenced to GND unless noted otherwise.
THERMAL INFORMATION
Rating Thermal Characteristic, QFN Package (Note 1) Operating Junction Temperature Range (Note 2) Operating Ambient Temperature Range Maximum Storage Temperature Range Moisture Sensitivity Level, QFN Package * The maximum package power dissipation must be observed. 1. JESD 51-5 (1S2P Direct-Attach Method) with 0 LFM. 2. JESD 51-7 (1S2P Direct-Attach Method) with 0 LFM. Symbol RqJA TJ TA TSTG MSL Value 30.5 0 to 125 0 to 70 -55 to +150 1 Unit C/W C C C
http://onsemi.com
7
NCP5393A
ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0CvTAv70C; 4.75 VvVCCv5.25 V; All DAC Codes; CVCC = 0.1 mF)
Parameter ERROR AMPLIFIERS (VDD & VDDNB) Input Bias Current Input Offset Voltage (Note 3) Open Loop DC Gain Open Loop Unity Gain Bandwidth Open Loop Phase Margin Slew Rate V+ = V- = 1.3V CL = 60 pF to GND, RL = 10 kW to GND CL = 60 pF to GND, RL = 10 kW to GND CL = 60 pF to GND, RL = 10 kW to GND DVIN = 100 mV, AV = -10 V/V, 1.5 V < VCOMP < 2.5 V, CL = 60 pF, DC Loading = $125 mA 10 mV of Overdrive, ISOURCE = 2.0 mA 10 mV of Overdrive, ISINK = 2.0 mA 10 mV of Overdrive, VOUT = 3.5 V 10 mV of Overdrive, VOUT = 1.0 V VS- Voltage at 0 V DRVON = Low DRVON = High VS+ Input Bias Voltage DRVON = Low DRVON = High VS+ Input Voltage Range (Note 3) VS- Input Voltage Range (Note 3) -3dB Bandwidth (Note 3) DC gain, VS+ to DIFFOUT DAC Accuracy (Measured at VS+) CL = 80 pF to GND, RL = 10 kW to GND VS+ to VS- = 0.5 V to 2.35 V Closed Loop Measurement, Error Amplifier Inside the Loop. 1.0125 V v VDAC v 1.5500 V 0.8000 V v VDAC v 1.0000 V 12.5 mV v VDAC v 0.8000 V DVIN = 100 mV, DVOUT = 1.3 V-1.2 V ISOURCE = 2 mA ISINK = 2 mA VOUT = 3 V VOUT = 0.5 V 0 mV < (CSx - CSxN) < 60 mV CSx = CSxN = 1.3 V CL = 20 pF to GND, RL = 1 kW to GND ISOURCE = 4.0 mA ISINK = 1.0 mA VOUT = 3.0 V VOUT = 1.0 V - 3.0 - - 5.7 2.0 2.0 2.0 0.5 0.982 -0.3 -0.3 -200 -1.0 - - - - 3.5 - - - - - 80 15 70 5 - - 2 2 200 1.0 - - - - - 1.0 - - nA mV dB MHz deg V/ms Test Conditions Min Typ Max Unit
Maximum Output Voltage Minimum Output Voltage Output Source Current (Note 3) Output Sink Current (Note 3)
V V mA mA
DIFFERENTIAL SUMMING AMPLIFIERS (VDD & VDDNB) VS- Input Bias Current VS+ Input Resistance 33 1.0 7 0.37 0.05 - - 15 1.0 1.022 3.0 0.3 V V MHz V/V V mA kW
-0.5 -5 -8
- - - 10
0.5 5 8
% mV mV V/ms V V mA mA
Slew Rate Maximum Output Voltage Minimum Output Voltage Output source current (Note 3) Output sink current (Note 3) DROOP AMPLIFIERS (VDD & VDDNB) Gain from Current Sense Input to Droop Amplifier Output Droop Amplifier DC Output Voltage Slew Rate Maximum Output Voltage Minimum Output Voltage Output Source Current (Note 3) Output Sink Current (Note 3)
6.0 1.3 5.0 - - 4.0 1.0
6.3
V/V V
- - 1.0 - -
V/ms V V mA mA
3. Guaranteed by design. Not production tested.
http://onsemi.com
8
NCP5393A
ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0CvTAv70C; 4.75 VvVCCv5.25 V; All DAC Codes; CVCC = 0.1 mF)
Parameter CURRENT SENSE AMPLIFIERS (VDD & VDDNB) Input Bias Current Common Mode Input Voltage Range Differential Mode Input Voltage Range (Note 3) Input Offset Voltage (Note 3) Gain from Current Sense Input to PWM Comparator INTERNAL OFFSET VOLTAGE Voltage at Error Amplifier Non-Inverting Inputs DRVON & NB_DRVON Output Voltage (High) Output Voltage (Low) Delay Time Active Internal Pull-up Resistance Active Internal Pull-down Resistance Rise Time Fall Time VDD PWM OSCILLATOR Switching Frequency Range Switching Frequency Accuracy 2- or 4-phase Switching Frequency Accuracy 3-phase ROSC Output Voltage VDDNB PWM OSCILLATOR Switching Frequency PWM COMPARATORS (VDD & VDDNB) Minimum Pulse Width (Note 3) Propagation Delay (Note 3) Magnitude of the PWM Ramp 0% Duty Cycle 100% Duty Cycle PWM Phase Angle Error PWRGOOD OUTPUT PWRGOOD Output Voltage (Low) PWRGOOD Rise Time PWRGOOD High-State Leakage IPGD = 5 mA External Pullup of 1 kW to 5 V CTOTAL = 45 pF, DVOUT = 10% to 90% VPWRGOOD = 5.25 V - - - - 125 - 0.4 - 1 V ns mA COMP Voltage at which the PWM Outputs Remain LOW COMP Voltage at which the PWM Outputs Remain HIGH Between Adjacent Phases FSW = 800 kHz $20 mV of Overdrive - - - - - -15 30 10 1.0 0.2 1.2 - - - - - +15 ns ns V V V - 1.25 - x fVDD ROSC = 49.9 kW ROSC = 24.9 kW ROSC = 10 kW ROSC = 49.9 kW ROSC = 24.9 kW ROSC = 10 kW 10 mA IROSC 200 mA 100 196 380 803 196 380 803 1.94 - - - - - - - 2.0 900 226 420 981 226 420 981 2.06 kHz kHz Sourcing 500 mA Sinking 500 mA Propagation Delays Sourcing 500 mA Sinking 500 mA CL (PCB) = 20 pF, DVOUT = 10% to 90% CL (PCB) = 20 pF, DVOUT = 10% to 90% 3.0 - - - - - - - - 10 2.0 150 130 15 - 0.7 - - - - - V V ns kW W ns ns - 1.3 - V CSx = CSxN = 1.00 V 0 mV < (CSx - CSxN) < 60 mV CSx = CSxN = 1.4 V -50 -0.3 -120 -1.0 5.0 - - - - 6.0 50 2.6 120 1.0 7.0 nA V mV mV V/V Test Conditions Min Typ Max Unit
kHz
V
3. Guaranteed by design. Not production tested.
http://onsemi.com
9
NCP5393A
ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0CvTAv70C; 4.75 VvVCCv5.25 V; All DAC Codes; CVCC = 0.1 mF)
Parameter PWRGOOD OUTPUT PWRGOOD Upper Threshold PWRGOOD Lower Threshold PWM OUTPUTS (VDD & VDDNB) Output Voltage (High) Output Voltage (Mid) Output Voltage (Low) Rise and Fall Times Tri-State Output Leakage Output Impedance - HIGH or LOW State Sourcing 500 mA RL = 4 kW to GND Sinking 500 mA CL = 50 pF, 0.7 V to 3.0 V or 3.0 V to 0.7 V Gx = 2.5 V (x = 1-4 or NB) Resistance to VCC or GND 3.0 1.3 - - -1.5 - - 1.5 - 15 - 50 VCC 1.7 0.15 - 1.5 - V V V ns mA W VOUT Increasing, DAC = 1.3 V (Wrt DAC) VOUT Decreasing, DAC = 1.3 V - - 300 350 - - mV mV Test Conditions Min Typ Max Unit
VDD REGULATOR 2/3/4 PHASE DETECTION Gate Pin Source Current Gate Pin Threshold Voltage Phase Detect Timer SLEW RATE LIMITERS Soft-Start Slew Rate Slew Rate Limit In Any Mode During Soft-Start In Any Mode after Soft-Start Completes 0.64 - 0.8 3.25 0.96 - mV/ms mV/ms - - - 80 250 20 - - - mA mV ms
VID INPUTS (Note: In SVI Mode, VID[2] = Bidirectional "SVD' Line and VID[3] = "SVC" Clock Input) VID Input Voltage (High) VID Input Voltage (Low) VID Hysteresis Input Pulldown Current SVD Output Voltage (Low) ENABLE INPUT ENABLE Input Voltage (High) ENABLE Input Voltage (Low) Enable Hysteresis Enable Input Pull-Up Current VFIXEN INPUT (Active-Low Input) VFIXEN Input Voltage (High) VFIXEN Input Voltage (Low) VFIXEN Hysteresis VFIXEN Input Pull-Up Current VHIGH VLOW Low - High or High - Low Internal Pullup to VCC Before Enable Assertion, No Phase Shedding while PSI_L Active. All Phases Operate in Diode Emulation Mode Before ENABLE Assertion, Phase Shed to 2 Phases Before ENABLE Assertion, Phase Shed to 1 Phase After Soft-Start, VHIGH After Soft-Start, VLOW - 0.9 - - - 100 15 - - 0.6 V V mV mA VHIGH VLOW Low - High or High - Low Internal Pullup to VCC 2.0 - - - - - 200 15 - 0.8 - - V V mV mA VHIGH VLOW VHIGH - VLOW or VLOW - VHIGH VIN = 0.6 V - 1.9 V In SVI Mode, ISINK = 5 mA 0.9 - - - 0 - - 100 15 - - 0.6 - - 0.25 V V mV mA V
PSI_L (Power Saving Phase Shed and Control, Active Low) (This pin is used in PVI mode only) PSI_L Phase Shed Count - - 0.6 V
PSI_L Phase Shed Count PSI_L Phase Shed Count PSI_L Input Voltage (High) PSI_L Input Voltage (Low)
0.9 1.3 0.9 -
- - - -
1.1 - - 0.6
V V V V
3. Guaranteed by design. Not production tested.
http://onsemi.com
10
NCP5393A
ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0CvTAv70C; 4.75 VvVCCv5.25 V; All DAC Codes; CVCC = 0.1 mF)
Parameter Test Conditions Min Typ Max Unit PSI_L (Power Saving Phase Shed and Control, Active Low) (This pin is used in PVI mode only) PSI_L Hysteresis CURRENT LIMIT Current Sense Amp to ILIM Gain ILIM Pin Input Bias Current ILIM Pin Working Voltage Range (Note 3) ILIM Offset Voltage Delay VDDNB Current Limit Coefficient = N x VNBILIM /VILIM, where N = number of VDD phases, and VNBILIM is the equivalent voltage threshold for NB Current Limit resulting from VILIM. Offset extrapolated to CSx-CSxN = 0 V, and referred to the ILIM pin 20 mV < (CSx - CSxN) < 60 mV (CS inputs tied) 5.7 - 0.2 - - 6.0 - - 30 600 1.0 6.3 0.5 2.0 - - V/V mA V mV ns V After Soft-Start, VHIGH - VLOW or VLOW - VHIGH 100 mV
OFFSET INPUTS (VDD & VDDNB) Output Offset Voltage Above VDAC OUTPUT OVERVOLTAGE PROTECTION (VDD & VDDNB) Over Voltage Threshold In normal operation, with no VID changes VDAC + 220 VDAC + 235 VDAC + 250 mV 0 - 800 mV
VCCA UNDERVOLTAGE PROTECTION VCCA UVLO Start Threshold VCCA UVLO Stop Threshold VCCA UVLO Hysteresis INPUT SUPPLY CURRENT VCC Operating Current 12VMON 12VMON (High Threshold) 12VMON (Low Threshold) 12VMON Hysteresis Low - High or High - Low 8 7 8.5 7.5 1.0 9 8 V V V ENABLE held Low, No PWM operation - 25 35 mA 4.0 3.8 4.25 4.05 200 4.5 4.3 V V mV
3. Guaranteed by design. Not production tested. 2.03
TYPICAL CHARACTERISTICS
1.5 1.4 1.3 1.2 1.1 1.0 Enable Decreasing Voltage Enable Increasing Voltage
2.01 SS TIME (ms)
1.99
1.97
1.95
0
25
50
75
EN, ENABLE THRESHOLD VOLTAGE (V)
0
25
50
75
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 1. SS Time vs. Temperature
Figure 2. Enable Threshold Voltage vs. Temperature
http://onsemi.com
11
NCP5393A
TYPICAL CHARACTERISTICS
26.1 DETECT THRESHOLD (mV) 0 25 50 75 25.8 ICC CURRENT (mA) 25.5 25.2 24.9 24.6 24.3 24.0 231.1 230.8 230.5 230.2 229.9 229.6 229.3 229.0 0 25 50 75
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 3. ICC Current vs. Temperature
VCCP UVLO THRESHOLD VOLTAGE (V) 4.5 VCCP Increasing Voltage 4.0 2.009 2.008 ROSC VOLTAGE (V) 2.007 2.006 2.005 2.004 3.0 2.003
Figure 4. 2/3/4 Phase Detection Threshold vs. Temperature
3.5
VCCP Decreasing Voltage
0
25
50
75
0
25
50
75
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 5. VCCP Undervoltage Lockout Threshold Voltage vs. Temperature
10 9.5 9.0 VCC Increasing Voltage 8.5 8.0 7.5 7.0 VCC Decreasing Voltage 370 360 350 340 330 320 310
Figure 6. ROSC Voltage vs. Temperature
PWRGOOD THRESHOLD VOLTAGE (mV)
VCC UVLO THRESHOLD VOLTAGE (V)
PWRGOOD Upper Voltage
PWRGOOD Lower Voltage 0 25 50 75
0
25
50
75
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 7. 12VMON Undervoltage Lockout Threshold Voltage vs. Temperature
Figure 8. PWRGOOD Voltage vs. Temperature
http://onsemi.com
12
NCP5393A
Functional Description
General
NCP5393A is a universal CPU hybrid power Controller compatible with both Parallel VID interface (PVI) and Serial VID interface (SVI) protocols for AMD Processors. The Controller implements a single-phase control architecture to provide the Northbridge (NB) voltage on the same chip. For the CORE section, programmable 2- to-4 phase featuring Dual-Edge multiphase architecture is implemented. It embeds two independent controllers for CPU CORE and the integrated NB, each one with its set of protections. The NCP5393A incorporates differential voltage sensing, differential phase current sensing, optional load-line voltage positioning, and programmable VDD and VDDNB offsets to provide accurately regulated power parallel- and serial-VID AMD processors. Dual-edge multiphase modulation provides the fastest initial response to dynamic load events. NCP5393A also supports V_FIX mode for board debug and testing. In this particular configuration the SVI bus is used as a static bus configuring four operative voltages (through SVC and SVD) for both the sections and ignoring any serial-VID command. NCP5393A is able to detect which kind of CPU is connected and configures itself to work as a Single-Plane PVI controller or Dual-Plane SVI controller.
Remote Output Sensing Amplifier (RSA)
Gate Driver Outputs and 2/3/4 Phase Operation
The part can be configured to run in 2-, 3-, or 4-phase mode. In 2-phase mode, phases 1 and 3 should be used to drive the external gate drivers, G2 and G4 must be grounded. In 3-phase mode, gate output G4 must be grounded. In 4-phase mode all 4 gate outputs are used as shown in the 4-phase Applications Schematic. The Current Sense inputs of unused channels should be connected to GND or to VDD. Please refer to table "PIN CONNECTIONS vs. PHASE COUNTS" for details.
Differential Current Sense Amplifiers and Summing Amplifier
A true differential amplifier allows the NCP5393A to measure Vcore voltage feedback with respect to the Vcore ground reference point by connecting the Vcore reference point to VSP, and the Vcore ground reference point to VSN. This configuration keeps ground potential differences between the local controller ground and the Vcore ground reference point from affecting regulation of Vcore between Vcore and Vcore ground reference points. The RSA also subtracts the DAC (minus VID offset) voltage, thereby producing an unamplified output error voltage at the DIFFOUT pin. This output also has a 1.3 V bias voltage as the floating ground to allow both positive and negative error voltages.
Precision Programmable DAC
Four differential amplifiers are provided to sense the output current of each phase. The inputs of each current sense amplifier must be connected across the current sensing element of the phase controlled by the corresponding gate output (G1, G2, G3, or G4). If a phase is unused, the differential inputs to that phase's current sense amplifier must be shorted together and connected to the GND or to VDD. The current signals sensed from inductor DCR are fed into a summing amplifier to have a summed-up output. The outputs of current sense amplifiers control three functions. First, the summing current signal of all phases will go through DROOP amplifier and join the voltage feedback loop for output voltage positioning. Second, the output signal from DROOP amplifier also goes to ILIM amplifier to monitor the output current limit. Finally, the individual phase current contributes to the current balance of all phases by offsetting their ramp signals of PWM comparators.
Oscillator and Triangle Wave Generator
A precision programmable DAC is provided and system trimmed. This DAC has 0.5% accuracy over the entire operating temperature range of the part. The NCP5393A is a Hybrid controller which supports both a six bit parallel VID interface (PVI) and a seven bit serial VID interface (SVI). The NCP5393A allows manufacturers to build a motherboard that will accommodate either parallel or serial VID processors in the same socket.
High Performance Voltage Error Amplifier
The error amplifier is designed to provide high slew rate and bandwidth. Although not required when operating as the controller of a voltage regulator, a capacitor from COMP to VFB is required for stable unity gain test configurations.
The controller embeds a programmable precision dual-Oscillator: one section is used for the CORE and it is a multiphase programmable oscillator managing equal phase-shift among all phases and the other section is used for the NB section. The oscillator's frequency is programmed by the resistance connected from the ROSC pin to ground. The user will usually form this resistance from two resistors in order to create a voltage divider that uses the ROSC output voltage as the reference for creating the current limit setpoint voltage. The oscillator frequency range is 100 kHz per phase to 1.0 MHz per phase. The oscillator generates up to 4 symmetrical triangle waveforms with amplitude between 1.3 V and 2.3 V. The triangle waves have a phase delay between them such that for 2-, 3- and 4-phase operation the PWM outputs are separated by 180, 120, and 90 angular degrees, respectively. When the NB phase is enabled, in order to ensure that the VDDNB oscillator does not accidentally lock to the VDD oscillator, the VDDNB oscillator will free-run at a frequency which is nominally 1.25 ratio of fVDD.
http://onsemi.com
13
NCP5393A
CPU Support
NCP5393A is able to detect the CPU it is going to supply and configure itself to PVI or SVI mode. When in PVI mode, to address the CORE section the NCP5393A uses VID[5:0]. When in SVI mode NCP5393A uses VID2 and VID3 alone for SVC and SVD information respectively. Whether the controller is controlled by the serial or parallel interface is determined by sampling the VID1 line at the time that the voltage regulator enable line is asserted; if the VID1 line is high when Enable is asserted, the voltage regulator starts in PVI mode, otherwise the voltage regulator starts in SVI mode.
PVI - Parallel Interface
* * * *
PVI is a 6-bit wide parallel interface to address the CORE Section reference. NB is kept in HiZ mode. Parallel mode operation is depicted in Figure 9. Voltage identifications for the 6bit AMD mode is given in Table 2. The normal PVI startup sequence for the NCP5393A is as follows: * 5 V is applied to the VCCA and VCCB pins to power the NCP5393A and 12 V is applied to 12VMON. * The NCP5393A samples the load on the G4 and G2 pins. If these pins are tied to ground the operating mode will be altered from four phase mode, to three phase, or two phase operation. * The system power sequence logic asserts the NCP5393A ENABLE pin:
- The NCP5393A will sample the VID1 line to determine whether to start in SVI or PVI mode. PVID mode is determined when VID1 = High. - The NCP5393A samples the voltage on the PSI_L pin in order to determine the desired operating configuration during power saving mode. - The Boot VID is captured from decoding the voltages on the VID[0:5]. The NCP5393A VDD regulator will soft-start and ramp to the initial Boot VID. The VDDNB regulator remains off (high-Z output). PWRGOOD is asserted by the NCP5393A. PWROK is not used in PVID mode. The NCP5393A will accept new VID codes on the parallel VID interface (See Table 2). See Figure 9 for details.
Table 1. Metal VID/BOOT VID
Output Voltage SVC 0 0 1 1 SVD 0 1 0 1 Pre-PWROK Metal VID 1.1 V 1.0 V 0.9 V 0.8 V
DC IN VDDIO ENABLE BOOT VID MSB VID[5] VR Turn-On Command
With ENABLE assertion, the PSI_L Phase Shed Strategy is Locked therefore Voltages on PSI_L must be stable prior to ENABLE assertion. VR Turn-Off Command
PVIEN/ VID[1] VID[0]
VID[1] High at Rise of Enable Selects PVI Operation BOOT VID LSB
At end of soft-start, PSI_L can be asserted. VDD ONLY [NDDNB N/A] PWRGOOD PWROK IS N/A Output Rises to BOOT VID at SS Rate Soft-Start is Complete Further VDD Transition(s) at Regular Slew Rate PWRGOOD De-Assertion Occurs on Faults Only
VR Turn-Off Command Forces PWRGOOD Low
Figure 9. Power Up Sequences in Parallel Mode Operation
http://onsemi.com
14
NCP5393A
Table 2. SIX-BIT PARALLEL VID CODES in PVI Modes
SVID[5:0] 00_0000 00_0001 00_0010 00_0011 00_0100 00_0101 00_0110 00_0111 00_1000 00_1001 00_1010 00_1011 00_1100 00_1101 00_1110 00_1111 VOUT (V) 1.5500 1.5250 1.5000 1.4750 1.4500 1.4250 1.4000 1.3750 1.3500 1.3250 1.3000 1.2750 1.2500 1.2250 1.2000 1.1750 SVID[5:0] 01_0000 01_0001 01_0010 01_0011 01_0100 01_0101 01_0110 01_0111 01_1000 01_1001 01_1010 01_1011 01_1100 10_1101 01_1110 01_1111 VOUT (V) 1.1500 1.1250 1.1000 1.0750 1.0500 1.0250 1.0000 0.9750 0.9500 0.9250 0.9000 0.8750 0.8500 0.8250 0.8000 0.7750 SVID[5:0] 10_0000 10_0001 10_0010 10_0011 10_0100 10_0101 10_0110 10_0111 10_1000 10_1001 10_1010 10_1011 10_1100 10_1101 10_1110 10_1111 VOUT (V) 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6325 0.6250 0.6125 0.6000 0.5875 0.5750 SVID[5:0] 11_0000 11_0001 11_0010 11_0011 11_0100 11_0101 11_0110 11_0111 11_1000 11_1001 11_1010 11_1011 11_1100 11_1101 11_1110 11_1111 VOUT (V) 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750
SVI - Serial Interface SVI is a two wire, Clock and Data, bus that connects a single master (CPU) to one NCP5393A. The master initiates and terminates SVI transactions and drives the clock, SVC, and the data SVD, during a transaction. The slave receives the SVI transactions and acts accordingly. SVI wire protocol is based on fast-mode I2C. PWROK is properitery of the SVI protocol and is considered at start-up. The SVI mode operation is explained in Figure 10. The VID codes from the decoded SVI value are given in Table 3. The normal SVI startup sequence for the NCP5393A is as follows: * 5 V is applied to the VCCA and VCCB pins to power the NCP5393A and 12 V is applied to 12VMON. * The NCP5393A samples the load on the G4 and G2 pins. If these pins are tied to ground the operating mode will be altered from four phase mode, to three phase, or two phase operation. * The system power sequence logic asserts the NCP5393A ENABLE pin:
* * * * *
- The NCP5393A will sample the VID1 line to determine whether to start in SVI or PVI mode. SVID mode is determined when VID1 = Low. - The NCP5393A samples the voltage on the PSI_L pin in order to determine the desired operating configuration during power saving mode. - The Boot VID is captured from decoding the voltages on the VID3/SVC and VID2/SVD pins per Table 1 and stored. The NCP5393A will start the VDD and VDDNB regulators. Both regulators will soft start and ramp to the Boot VID Voltage (See Table 1). The NCP5393A asserts PWRGOOD. The system asserts PWROK The system processor will hold the boot VID voltage for at least 10us after PWROK signal is asserted Now the NCP5393A can accept new SVID codes on the serial VID interface (See Table 3). If the system should de-assert PWROK, then the NCP5393A will reset the Core and Northbridge VIDs and regulate at the Boot VID voltage.
http://onsemi.com
15
NCP5393A
Table 3. SEVEN-BIT SERIAL VID CODES for SVI Mode
SVID[6:0] 000_0000 000_0001 000_0010 000_0011 000_0100 000_0101 000_0110 000_0111 000_1000 000_1001 000_1010 000_1011 000_1100 000_1101 000_1110 000_1111 001_0000 001_0001 001_0010 001_0011 001_0100 001_0101 001_0110 001_0111 001_1000 001_1001 001_1010 001_1011 001_1100 001_1101 001_1110 001_1111 VOUT (V) 1.5500 1.5375 1.5250 1.5125 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 SVID[6:0] 010_0000 010_0001 010_0010 010_0011 010_0100 010_0101 010_0110 010_0111 010_1000 010_1001 010_1010 010_1011 010_1100 010_1101 010_1110 010_1111 011_0000 011_0001 011_0010 011_0011 011_0100 011_0101 011_0110 011_0111 011_1000 011_1001 011_1010 011_1011 011_1100 011_1101 011_1110 011_1111 VOUT (V) 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 SVID[6:0] 100_0000 100_0001 100_0010 100_0011 100_0100 100_0101 100_0110 100_0111 100_1000 100_1001 100_1010 100_1011 100_1100 100_1101 100_1110 100_1111 101_0000 101_0001 101_0010 101_0011 101_0100 101_0101 101_0110 101_0111 101_1000 101_1001 101_1010 101_1011 101_1100 110_1101 101_1110 101_1111 VOUT (V) 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6325 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 SVID[6:0] 110_0000 110_0001 110_0010 110_0011 110_0100 110_0101 110_0110 110_0111 110_1000 110_1001 110_1010 110_1011 110_1100 110_1101 110_1110 110_1111 111_0000 111_0001 111_0010 111_0011 111_0100 111_0101 111_0110 111_0111 111_1000 111_1001 111_1010 111_1011 111_1100 111_1101 111_1110 111_1111 VOUT (V) 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 OFF OFF OFF OFF
http://onsemi.com
16
NCP5393A
DC IN VDDIO ENABLE PVIEN/ VID[1] SVC/ VID[3] SVD/ VID[2] BOOT VID LSB VDD and VDDNB PWRGOOD PWROK Soft-Start is Complete CPU Can Begin Serial Data Xfer Outputs Rise to BOOT VID at SS Rate Possible PWRGOOD De-Assertion System Power Fault - Revert to BOOT VID Resume Serial VID Transactions At end of soft-start, PSI_L can be asserted through the SVID protocal. PWRGOOD De-Assertion Causes System PWROK De-Assertion VID[1] Low at Rise of Enable Selects SVI Operation BOOT VID MSB VR Turn-On Command With ENABLE assertion, the PSI_L Phase Shed Strategy is Locked therefore Voltages on PSI_L must be stable prior to ENABLE assertion. VR Turn-Off Command
VR Turn-Off Command Forces PWRGOOD Low
Figure 10. Power-Up Sequence in Serial Mode Operation Hardware Jumper Override - V_FIX
VFIX is an active low pin and when it is pulled low, the controller enters V_FIX mode.The voltage regulator can be powered when an external SVI bus master is not present. When in VFIX mode, all of the voltage regulator's output voltages will be governed by the information shown in Table 4, regardless of the state of PWROK. VFIX mode is for debug only. If VFIX mode is necessary for processor bring-up, VFIXEN, SVC, and SVD should be connected with jumpers to either ground or VDDIO through suitable pull-up resistors. SVC and SVD are considered as static VID and the output voltage will change according to their status.
Table 4. SVI VFIX VID CODES (TWO-BIT PARALLEL)
SVC 0 0 1 1 SVD 0 1 0 1 VOUT (V) 1.4 1.2 1.0 0.8
* The system power sequence logic asserts the
* * * * *
The normal VFIXEN startup sequence for the NCP5393A is as follows: * 5 V is applied to the VCCA and VCCB pins to power the NCP5393A and 12 V is applied to 12VMON. * The NCP5393A samples the load on the G4 and G2 pins. If these pins are tied to ground the operating mode will be altered from four phase mode, to three phase, or two phase operation.
NCP5393A ENABLE pin: - The NCP5393A will sample the VID1 line to determine whether to start in SVI or PVI mode. - The NCP5393A samples the voltage on the PSI_L pin in order to determine the desired operating configuration during power saving mode. - The Boot VID is dependent on SVI or PVI mode startup. The NCP593A VDD regulator (and VDDNB if in SVID mode) will soft-start and ramp to the initial Boot VID. VFIXEN mode is entered once VFIXEN is asserted and the VDD and VDDNB regulators will regulate to the VFIXEN VID. VFIXEN VID is captured from decoding the voltages on the VID3/SVC and VID2/SVD pins per Table 4. If VFIXEN is asserted prior to the VID controller reaching the Boot VID, the VID controller will move to the VFIXEN VID. If VFIXEN is de-asserted, the evice PORs. This occurs independent of ENABLE.
PWROK De-Assertion
Anytime PWROK de-asserts while EN is asserted, the controller uses the previously stored BOOT VID and regulates all planes to that level performing an on-the-Fly transition to that level. PWRGOOD remains asserted in this process.
http://onsemi.com
17
NCP5393A
Power Saving Indicator (PSI_L) and Phase Shedding
An AMD PVID processor provides an output signal to the NCP5393A controller's PSI_L input to indicate when the processor is in a low power state. An AMD SVID processor indicates PSI_L mode through the SVID protocol. The NCP5393A uses PSI_L assertion to maximize efficiency at light loads. When PSI_L is asserted, the PSI_L function will be enabled, and the NCP5393A will run with a reduced phase count. The number of phases in PSI_L mode is determined by the voltage level present on the PSI_L input upon ENABLE assertion. This detection of phase count applies for both PVID and SVID AMD processors. In power saving mode, the NCP5393A works with the NCP5359A driver to emulate diode conduction mode at light load for further power saving. Protection Features: The NCP5393A handles many protection features. Undervoltage lockout, Over current shutdown, Overvoltage, Under voltage, Soft-Start etc are the main features. All the fault responses of the NCP5393A are listed in Table 5.
Undervoltage Lockout
overcurrent latch is set when the current information exceeds the voltage at the ILIM pin. The outputs are pulled low, and the soft-start is pulled low. The outputs will remain disabled until the VCC voltage is removed and re-applied, or the ENABLE input is brought low and then high. The NCP5393A handles Core per-phase Over-Current also. If Over-Current is detected in a phase, then the PWM of that phase will be turned off. Cycle-by-cycle current limit protection is implemented for per-phase Over-Current in the NCP5393A. DRVON never goes low due to per-phase current trip. NB Over current is handled in similar way as the global CORE Over current. The total output current is compared with Ilimit * 1.0. When Over-current occurs in the NB, NB-DRVON is pulled low.
Output Overvoltage and Undervoltage Protection and Power Good Monitor
An undervoltage lockout (UVLO) senses the VCC and VCCP input. During powerup, the input voltage to the controller is monitored, and the PWM outputs and the soft-start circuit are disabled until the input voltage exceeds the threshold voltage of the UVLO comparator. The UVLO comparator incorporates hysteresis to avoid chattering, since VCC is likely to decrease as soon as the converter initiates soft-start.
Overcurrent Shutdown
A programmable overcurrent function is incorporated within the IC. A comparator and latch make up this function. The inverting input of the comparator is connected to the ILIM pin. The voltage at this pin sets the maximum output current the converter can produce. The ROSC pin provides a convenient and accurate reference voltage from which a resistor divider can create the overcurrent setpoint voltage. Although not actually disabled, tying the ILIM pin directly to the ROSC pin sets the limit above useful levels - effectively disabling overcurrent shutdown. The comparator noninverting input is the summed current information from the VDRP minus offset voltage. The
An output voltage monitor is incorporated. During normal operation, if the output voltage is 250 mV over the DAC voltage, the PWRGOOD goes low, the DRVON signal remains high, the PWM outputs are set low. The outputs will remain disabled until the VCC voltage is removed and reapplied. Every time the OV is triggered it will increment the OV counter. If the counter reaches a count of 16 then the OV condition will latch into a permanent OV state. It will require POR or disable/enable to restart. Prior to latching if the OV condition goes away then normal operation will resume. An OV decrement counter is also incorporated. It consists of a free-running clock which runs at 8x the PWM frequency. So essentially every 4096 PWM cycles the OV counter will decrement. For example, for a max PWM frequency of 1 MHz, the counter decrements roughly every 4 ms and for a PWM frequency of 400 kHz, it would be about every 10 ms. During normal operation, if the output voltage falls more than 350 mV below the DAC setting, the PWRGOOD pin will be set low until the output voltage rises.
Soft-Start
The NCP5393A ramps VDD (and VDDNB in SVID mode) to the Boot VID at a soft-start rate of 0.8 mV/ms typical. Upon receiving a PVID or SVID code (after PWROK assertion) the outputs ramp to the final DAC setting at the Dynamic VID slew rate of 3.25 mV/ms. Typical soft-start sequence timing is shown in Figure 11.
http://onsemi.com
18
NCP5393A
VID Setting Boot Voltage VOLTAGE NCP5393A Soft-Start Slew Rate 0.8 mV/ms NCP5393A Internal Dynamic VID Slew Rate 3.25 mV/ms
TIME
Figure 11. Soft Start Sequence to VCORE Table 5. FAULT RESPONSES
CONDITION VDD Global OCP PWM OUTPUT(s) All to High-Z PWRGOOD Latched Low DRVON (VDD) Latched Low DRVON (NB) Latched Low RESET METHOD Cycle ENABLE or +5 V and +12 V Cycle ENABLE or +5 V and +12 V May eventually cause a Global OCP or Output UV. NOTES
NB OCP
All to High-Z
Latched Low
Latched Low
Latched Low
VDD Per-Phase Current Limit Output OVP - Infrequent Output OVP - Frequent Output UV Monitor Unused Phase of VDD Regulator VDDNB Disabled 5 V UVLO
Affected phase set to Low or Mid state Held Low for duration of OV Latched Low
Unaffected
Unaffected
Unaffected
Held Low for duration of OV plus 500 ms Latched Low
Unaffected
Unaffected
"Infrequent" = fewer than 17 events per 4096/Fpwm seconds (e.g., 4.096 ms at Core PWM = 1 MHz) Cycle ENABLE, VCC (5 V) or 12 VMON "Frequent" = 17 or more events per 4096/Fpwm seconds (e.g., 4.096 ms at Core PWM = 1 MHz)
Unaffected
Unaffected
Unaffected
Held Low for duration of UV Unaffected
Unaffected
Unaffected
Set to High-Z
Unaffected
Unaffected
Set to High-Z All to High-Z
Unaffected by NB status Held Low
Unaffected Low until 5 V and 12 V are OK Low until 5 V and 12 V are OK
Latched Low Low until 5 V and 12 V are OK Low until 5 V and 12 V are OK Raise +5 V above UVLO Threshold Raise +12 V above UVLO Threshold 5 V and 12 V UVLO are the only modes which will force re-evaluating the phase count. 5 V and 12 V UVLO are the only modes which will force re-evaluating the phase count.
12 V UVLO
All to High-Z
Held Low
http://onsemi.com
19
NCP5393A
Table 5. FAULT RESPONSES
CONDITION DRVON is Pulled Low by External Means NB_DRVON is Pulled Low by External Means ENABLE is Low PWM OUTPUT(s) Unaffected (See Notes ) PWRGOOD Held Low DRVON (VDD) While Low a weak pull-up turns on DRVON (NB) Unaffected RESET METHOD Address underlying cause, and let DRVON go High Address underlying cause, and let NB_DRVON go High Assert ENABLE High NOTES VDD will try to regulate to 0 V. DRVON low will cause VDD MOSFETs to turn off. Both VDD & VDDNB will go through a SS upon recovery. VDDNB will try to regulate to 0 V. With NB_DRVON Low, all VDDNB MOSFETs to turnoff. Both VDD & VDDNB will go through a SS upon recovery. Cycling ENABLE does not cause the NCP5393A to re- evaluate the programmed number of phases
Unaffected (See Notes )
Held Low
Unaffected
While Low a weak pull-up turns on
All to High-Z
Held Low
Held Low
Held Low
http://onsemi.com
20
NCP5393A
Programming the Current Limit and the Oscillator Frequency The demo board is set for an operating frequency of approximately 330 kHz. The ROSC pin provides a 2.0 V reference voltage which is divided down with a resistor divider and fed into the current limit pin ILIM. Calculate the total series resistance to set the frequency and then calculate the individual RLIM1 and RLIM2 values for the divider. The series resistors RLIM1 and RLIM2 sink current from the ILIM pin to ground. This current is internally mirrored into a capacitor to create an oscillator. The period is proportional to the resistance and frequency is inversely proportional to the total resistance. The total resistance may be estimated by Equation 2. This equation is valid for the individual phase frequency in both three and four phase mode.
RTOTAL ^ 24686 30.5 * kW ^ 24686 Fsw-1.1549
(eq. 1)
330-1.1549
Figure 12. ROSC vs. Frequency
The current limit function is based on the total sensed current of all phases multiplied by a gain of 6. DCR sensed inductor current is function of the winding temperature. The best approach is to set the maximum current limit based on Calculate the current limit voltage:
VILIMIT ^ 6 * IMIN_OCP * DCRTmax )
the expected average maximum temperature of the inductor windings.
DCRTmax + DCR25C * (1 ) 0.00393 (T max -25)) * Vin-Vout * (N-1) * Vout L L
(eq. 2)
DCRTmax * Vout 2 * Vin * Fsw
(eq. 3)
Solve for the individual resistors:
RLIM2 + VILIMIT * RTOTAL 2*V
(eq. 4)
RLIM1 + RTOTAL-RLIM2
(eq. 5)
Final Equation for the Current Limit Threshold ILIMIT(Tinductor) ^
2 * V * RLIM2 RLIM1)RLIM2
6 * (DCR25C * (1 ) 0.00393(TInductor-25)))
*
Vout * Vin-Vout * (N-1) * Vout L L 2 * Vin * Fsw
(eq. 6)
The inductors on the demo board have a DCR at 25C of 0.75 mW. Selecting the closest available values of 16.9 kW for RLIM1 and 13.7 kW for RLIM2 yield a nominal operating frequency of 330 kHz and an approximate current
limit of 152 A at 100C. The total sensed current can be observed as a scaled voltage at the VDRP pin added to a positive, no-load offset of approximately 1.3 V.
http://onsemi.com
21
NCP5393A
OUTPUT OFFSET VOLTAGES
External offset voltages from 0 mv to 800 mV `above the DAC' can be added for the VDD and VDD_NB independently. Offset is set by a resistor divider from VCC to GND. Output offsets are ratiometric to VCC. As VCC changes, the on-chip scaling factors change by the same amount: Offset = 0.8 V x VOFFSET/VCC For example: For 0 V offset: pin voltage = GND; For 800 mV offset: pin voltage = VCC
Minimum Voffset_IN (as Vin/Vcc) 0 0.046875 0.078125 0.109375 0.140625 0.171875 0.203125 0.234375 0.265625 0.296875 0.328125 0.359375 0.390625 0.421875 0.453125 0.484375 0.515625 0.546875 0.578125 0.609375 0.640625 0.671875 0.703125 0.734375 0.765625 0.796875 0.828125 0.859375 0.890625 0.921875 0.953125 0.984375 Typical Voffset_IN (as Vin/Vcc) 0 0.06250 0.09375 0.12500 0.15625 0.18750 0.21875 0.25000 0.28125 0.31250 0.34375 0.37500 0.40625 0.43750 0.46875 0.50000 0.53125 0.56250 0.59375 0.62500 0.65625 0.68750 0.71875 0.75000 0.78125 0.81250 0.84375 0.87500 0.90625 0.93750 0.96875 1.00000 Maximum Voffset_IN (as Vin/Vcc) 0.046875 0.078125 0.109375 0.140625 0.171875 0.203125 0.234375 0.265625 0.296875 0.328125 0.359375 0.390625 0.421875 0.453125 0.484375 0.515625 0.546875 0.578125 0.609375 0.640625 0.671875 0.703125 0.734375 0.765625 0.796875 0.828125 0.859375 0.890625 0.921875 0.953125 0.984375 Vcc+0.3V Resulting Output Offset 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 550 575 600 625 650 675 700 725 750 800 Units mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV
The input to the OFFSET pin for the VDD output is encoded by an internal ADC. The input to the NB_OFFSET pin for the VDDNB output is encoded by the same ADC. The reference for this ADC is VCC. The ADC's output is ratiometric to VCC. Voffset IN represents the voltage applied to the OFFSET or NB_OFFSET pin. It is intended that these voltages be derived by a resistive divider from Vcc. The recommended total driving impedance is <10 kilohms.
http://onsemi.com
22
NCP5393A
In some modes, significant offset above VDAC could cause unpredictable results, or be harmful. The NCP5393A avoids such modes.
MODE PVI (Soft-Start) PVI (Normal Operation) SVI (Soft-Start) SVI (Boot VID) SVI (Normal Operation) VFIX VDD OFFSET NO YES NO NO YES NO NB OFFSET N/A N/A NO NO YES NO NOTES Soft-Start is to Boot VID; NB is OFF Open it up for testing and gaming. Soft-Start is to Boot VID; NB is ON Boot VID is AMD's start-up value Open it up for testing and gaming. VFIX is a special test mode
http://onsemi.com
23
NCP5393A
PACKAGE DIMENSIONS
QFN48 7x7, 0.5P CASE 485AJ-01 ISSUE O
D
PIN 1 LOCATION
AB
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO THE PLATED TERMINAL AND IS MEASURED ABETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 7.00 BSC 5.00 5.20 7.00 BSC 5.00 5.20 0.50 BSC 0.20 --- 0.30 0.50
2X
0.15 C
2X DETAIL A OPTIONAL CONSTRUCTION 2X SCALE
0.15 C 0.05 C 0.08 C
NOTE 4
DETAIL A 13 12
48X
L
The products described herein (NCP5393A), may be covered by one or more of the following U.S. patents, #US07057381. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EEE EEE EEE
TOP VIEW (A3) A1 SIDE VIEW D2
25
E L
A C
SEATING PLANE
SOLDERING FOOTPRINT*
5.20 1
2X
K
2X
7.30
E2
0.63
48X
1 48 37
36
0.30 b 0.10 C A B 0.05 C
NOTE 3
48X
0.50 PITCH
DIMENSIONS: MILLIMETERS
e e/2 BOTTOM VIEW
48X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
24
NCP5393A/D

▲Up To Search▲

Price & Availability of NCP5393A

	To Download NCP5393A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .